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commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 1 december 2004 IDTCV125 commercial temperature range programmable flexpc clock for p4 processor sm bus controller sel 100/96mhz control logic src clk output buffer stop logic 48mhz/96mhz output buffer sdata sclk v tt_ p wrgd #/pd fsa.b.c i ref src[6:1] 48mhz dot96 pll3 ssc n programmable pll4 pci[3:0], pcif[1:0] xtal osc amp cpu clk output buffer stop logic x1 x2 i ref cpu[1:0] ref cpu_itp/src7 pll1 ssc n programmable itp_en pci_stop# cpu_stop# lvds pll2 ssc sel100/96# lvds clk output buffer stop logic i ref the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc 6552/14 features: ? power management control suitable for notebook applications ? one high precision pll for cpu, ssc and n programming ? one high precision pll for src/pci, supports 100mhz output frequency, ssc and n programming ? one high precision pll for lvds. supports 100/96mhz output frequency, ssc programming ? one high precision pll for 96mhz/48mhz ? band-gap circuit for differential outputs ? support spread spectrum modulation, ?0.5 down spread and others ? support smbus block read/write, index read/write ? selectable output strength for ref ? allows for cpu frequency to change to a slower frequency to conserve power when an application is less execution- intensive ? smooth transition for n programming ? available in tssop package functional block diagram description: IDTCV125 is a 56 pin clock device, incorporating both intel ck410m and cksscd requirements, for intel advance p4 processors. the cpu output buffer is designed to support up to 400mhz processor. this chip has four plls inside for cpu, src/pci, lvds, and 48mhz/dot96 io clocks. this device also implements band-gap referenced i ref to reduce the impact of v dd variation on differential outputs, which can provide more robust system performance. static pll frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. each cpu/src/lvds has its own spread spectrum selection. outputs: ? 2*0.7v current ?mode differential cpu clk pair ? 6*0.7v current ?mode differential src clk pair ? one cpu_itp/src selectable clk pair ? 6*pci, 2 free running, 33.3mhz ? 1*96mhz, 1*48mhz ? 1*ref ? one 100/96 mhz differential lvds key specification: ? cpu/src clk cycle to cycle jitter < 85ps ? pci clk cycle to cycle jitter < 250ps ? static pll frequency divide error < 114 ppm ? static pll frequency divide error for 48mhz < 5 ppm
commercial temperature range 2 IDTCV125 programmable flexpc clock for p4 processor pin configuration symbol description min max unit v dda 3.3v core supply voltage 4.6 v v ddin 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. tssop top view 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pci0 pci_stop# cpu_stop# fsc/test_sel ref v ss _ref xtal_in xtal_out v dd _ref sda scl v ss _cpu cpu0 cpu0# v dd _cpu cpu1 cpu1# i ref v ssa v dda cpu2_itp/src7 cpu2_itp#/src7# v dd _src src6# src5 src5# v ss _src 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v dd _pci v ss _pci pci1 pci2 pci3 v ss _pci v dd _pci pcif0 /itp _ en pcif1/sel100/96# lvds v dd 48 usb48/fsa v ss 48 dot96 dot96# fsb/test_mode lvds# src1 src1# v dd _src src2 src2# src3 src3# src4 src4# v dd _src src6 v tt _p wrgd# / pd (1) (2) (2) frequency selection table fsc, b, a cpu src[7:0] pci usb dot ref 101 100 100 33.3 48 96 14.318 001 133 100 33.3 48 96 14.318 011 166 100 33.3 48 96 14.318 010 200 100 33.3 48 96 14.318 000 266 100 33.3 48 96 14.318 100 333 100 33.3 48 96 14.318 110 400 100 33.3 48 96 14.318 111 reserve 100 33.3 48 96 14.318 notes: 1. 130k internal pull-up resistor. 2. can be configured as 100mhz or 96mhz output clock, depending on pin9 power on pull-up (100mhz) or pull-down (96mhz) latch. if using internal pull-up resistor, power on would be 100mhz.
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 3 pin description pin number name type description 1v dd _pci pwr 3.3v 2v ss _pci gnd gnd 3 pci1 out pci clock 4 pci2 out pci clock 5 pci3 out pci clock 6v ss _pci gnd gnd 7v dd _pci pwr 3.3v 8 pcif0/itp_en i/o pci clock, free running. cpu2 select (sampled on v tt _p wrgd # assertion) high = cpu2. 9 pcif1/sel100/96# i/o pci clock, free running. sel100/96mhz (sampled on v tt _p wrgd # assertion) high, lvds = 100mhz. 10 v tt _p wrgd #/pd i n level-sensitive strobe used to latch the fsa, fsb, fsc/test_sel, and pcif0/itp_en inputs. after v tt _p wrgd # assertion, becomes a real-time input for asserting power down. (active high). latch pcif1/ sel100/96# input. 11 v dd 48 pwr 3.3v 12 usb48/fsa i/o 48mhz clock/fsa for cpu frequency selection 13 v ss 48 gnd gnd 14 dot96 out 96mhz 0.7 current mode differential clock output 15 dot96# out 96mhz 0.7 current mode differential clock output 16 fsb/test_mode in cpu frequency selection. selects r ef /n or hi-z when in test mode, hi-z = 1, r ef /n = 0. 17 lvds out differential serial reference clock 18 lvds# out differential serial reference clock 19 src1 out differential serial reference clock 20 src1# out differential serial reference clock 21 v dd _src pwr 3.3v 22 src2 out differential serial reference clock 23 src2# out differential serial reference clock 24 src3 out differential serial reference clock 25 src3# out differential serial reference clock 26 src4 out differential serial reference clock 27 src4# out differential serial reference clock 28 v dd _src pwr 3.3v 29 v ss _src gnd gnd 30 src5# out differential serial reference clock 31 src5 out differential serial reference clock 32 src6# out differential serial reference clock 33 src6 out differential serial reference clock 34 v dd _src pwr 3.3v 35 cpu2_itp#/src7# out selectable cpu or src differential clock output. itp_en = 0 at v tt _p wrgd # assertion = src7#. 36 cpu2_itp/src7 out selectable cpu or src differential clock output. itp_en = 0 at v tt _p wrgd # assertion = src7. 37 v dda pwr 3.3v 38 v ssa gnd gnd 39 i ref out reference current for differential output buffer 40 cpu1# out host 0.7 current mode differential clock output 41 cpu1 out host 0.7 current mode differential clock output 42 v dd _cpu pwr 3.3v
commercial temperature range 4 IDTCV125 programmable flexpc clock for p4 processor pin description (cont.) pin number name type description 43 cpu0# out host 0.7 current mode differential clock output 44 cpu0 out host 0.7 current mode differential clock output 45 v ss _cpu gnd gnd 46 scl in sm bus clock 47 sda i/o sm bus data 48 v dd _ref pwr 3.3v 49 xtal_out out xtal output 50 xtal_in i n xtal input 51 v ss _ref gnd gnd 52 ref out 14.318 mhz reference clock output 53 fsc/test_sel in cpu frequency selection. selects test mode if pulled above 2v when v tt _p wrgd # is asserted low. 54 cpu_stop# in stop all stoppable cpu clk 55 pci_stop# in stop all stoppable pci, src clk 56 pci0 out pci clock index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20-27 8 master byte count, n (0 is not valid) 28 1 slave ack (acknowledge) 29-36 8 master first data byte (offset data byte) 37 1 slave ack (acknowledge) 38-45 8 master 2nd data byte 46 1 slave ack (acknowledge) : master nth data byte slave acknowledge master stop index block read protocol master can stop reading any time by issuing the stop bit without waiting until nth byte (byte count bit30-37). bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave ack (acknowledge) 11-18 8 master register offset byte (starting byte) 19 1 slave ack (acknowledge) 20 1 master repeated start 21-28 8 master d3h 29 1 slave ack (acknowledge) 30-37 8 slave byte count, n (block read back of n bytes), power on is 8 38 1 master ack (acknowledge) 39-46 8 slave first data byte (offset data byte) 47 1 master ack (acknowledge) 48-55 8 slave 2nd data byte ack (acknowledge) : master ack (acknowledge) slave nth data byte not acknowledge master stop index byte write setting bit[11:18] = starting address, bit[20:27] = 01h. index byte read setting bit[11:18] = starting address. after reading back the first data byte, master issues stop bit.
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 5 ssc magnitude control for cpu, src, and smc smc[2:0] 000 -0.25 001 -0.5 010 -0.75 011 -1 100 0.125 101 0.25 110 0.375 111 0.5 sel 100/96# configuration sel 100/96# lvds frequency unit 0 96 mhz 1 100 m h z spread spectrum control selection (ssc) for lvds s[3:0] spread 0000 -0.8% 0001 - 1 % 0010 -1.25% 0011 -1.5% 0100 -1.75 % 0101 -2% 0110 -0.3% 0111 -0.5% 1000 0.3 % 1001 0.4 % 1010 0.5 % 1011 0.6 % 1100 0.8 % 1101 1 % 1110 1.25 % 1111 1.5% s.e. clock strength selection (pci, ref, usb48) str[1:0] level 00 1 01 0.8 10 0.6 11 1.2 resolution cpu (mhz) resolution n = 100 0.666667 150 133 0.666667 200 166 1.333333 125 200 1.333333 150 266 1.333333 200 333 2.666667 125 400 2.666667 150
commercial temperature range 6 IDTCV125 programmable flexpc clock for p4 processor byte 0 bit output(s) affected description/function 0 1 type power on 0 reserved 1 src1, src1# output enable tristate enable rw 1 2 src2, src2# output enable tristate enable rw 1 3 src3, src3# output enable tristate enable rw 1 4 src4, src4# output enable tristate enable rw 1 5 src5, src5# output enable tristate enable rw 1 6 src6, src6# output enable tristate enable rw 1 7 cpu2, cpu2#/ output enable tristate enable rw 1 src7, src7# byte 1 bit output(s) affected description/function 0 1 type power on 0 cpu[2:0], src[7:1], spread spectrum mode enable spread off spread on rw 0 pci[5:0], pcif[1:0] 1 cpu0, cpu0# output enable tristate enable rw 1 2 cpu1, cpu1# output enable tristate enable rw 1 3 reserved rw 0 4 ref output enable tristate enable rw 1 5 usb48 output enable tristate enable rw 1 6 dot96 output enable tristate enable rw 1 7 pcif0 output enable tristate enable rw 1 byte 2 bit output(s) affected description/function 0 1 type power on 0 pcif1 output enable tristate enable rw 1 1 reserved rw 1 2 pci0 output enable tristate enable rw 1 3 pci1 output enable tristate enable rw 1 4 pci2 output enable tristate enable rw 1 5 pci3 output enable tristate enable rw 1 6 reserved rw 1 7 reserved rw 1 control registers n programming procedure ? use index byte write. for n programming, the user only needs to access byte 11, byte 12, and byte 9. 1. write byte 11 for cpu pll n, cpu f = n* resolution (see resolution table). 2. write byte 12 for src pll n, src f = n*0.666667, pci = src f /3. 3. enable n programming bit, byte 9 bit 1. once this bit is enabled, any n value will be changed on the fly.
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 7 byte 3 bit output(s) affected description / function 0 1 type power on 0 reserved rw 0 1 src1 rw 0 2 src2 rw 0 3 src3 allow controlled by free running, not stopped with rw 0 4 src4 pci_stop# assertion affected by pci_stop# pci_stop# rw 0 5 src5 rw 0 6 src6 rw 0 7 src7 rw 0 byte 5 bit output(s) affected description / function 0 1 type power on 0 cpu0, cpu0# cpu0 pd drive mode driven in power down tristate in power down rw 0 1 cpu1, cpu1# cpu1 pd drive mode driven in power down tristate in power down rw 0 2 cpu2, cpu2# cpu2 pd drive mode driven in power down tristate in power down rw 0 3 src[7:1], src[7:1]# src pd drive mode driven in power down tristate in power down rw 0 4 cpu0, cpu0# cpu0 cpu_stop drive mode driven in cpu_stop# tristate when stopped rw 0 5 cpu1, cpu1# cpu1 cpu_stop drive mode driven in cpu_stop# tristate when stopped rw 0 6 cpu2, cpu2# cpu2 cpu_stop drive mode driven in cpu_stop# tristate when stopped rw 0 7 src[7:1], src[7:1]# src pci_stop drive mode driven in pci_stop tristate when stopped rw 0 byte 4 bit output(s) affected description / function 0 1 type power on 0 cpu0, cpu0# allow control of cpu0 not stopped stopped with rw 1 with assertion of cpu_stop# by cpu_stop# cpu_stop# 1 cpu1, cpu1# allow control of cpu1 not stopped stopped with rw 1 with assertion of cpu_stop# by cpu_stop# cpu_stop# 2 cpu2, cpu2# allow control of cpu2 not stopped stopped with rw 1 with assertion of cpu_stop# by cpu_stop# cpu_stop# 3 pcif0 allow controlled by not stopped stopped with rw 0 4 pcif1 pci_stop# assertion by pci_stop# pci_stop# rw 0 5 reserved rw 0 6 dot96 dot96 power down drive mode driven in power down tristate rw 0 7 reserved rw 0
commercial temperature range 8 IDTCV125 programmable flexpc clock for p4 processor byte 6 bit output(s) affected description / function 0 1 type power on 0 cpu[2:0] fsa latched value on power up r 1 cpu[2:0] fsb latched value on power up r 2 cpu[2:0] fsc latched value on power up r 3 pci, src software pci_stop control for stop all pci, pcif, and software stop rw 1 pci and src clk src which can be stopped disabled by pci_stop# 4 ref ref drive strength 1x drive 2x drive rw 1 5 reserved rw 0 6 test clock mode entry control normal operation test mode, controlled rw 0 by byte 6, bit 7 7 cpu, src, pci only valid when byte 6, bit 6 hi-z ref/n rw 0 pcif, ref, is high usb48, dot96 byte 7 bit output(s) affected description / function 0 1 type power on 0 vendor id r 1 1 vendor id r 0 2 vendor id r 1 3 vendor id r 0 4 revision id r 0 5 revision id r 0 6 revision id r 0 7 revision id r 0 byte 8, lvds control byte bit output(s) affected description/function 0 1 type power on 0 lvds hw/ smbus control hw (1) sw rw 0 1 lvds ssc en spread spectrum enable off on rw 1 2 lvds enable output enable disable enable rw 1 3 sel 100/96# select lvds frequency 96mhz 100mhz rw sel 100/96# 4 s3 see ssc table rw 0 5 s2 see ssc table rw 0 6 s1 see ssc table rw 0 7 s0 see ssc table rw 0 note: 1. if bit 0 is set to 0, lvds output frequency is selected by hw sel 100/96#. if bit 0 is set to 1, lvds output frequency is se lected by bit 3.
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 9 byte 9 bit output(s) affected description / function 0 1 type power on 0 one cycle read disable enable rw 0 1 n programming enable disable enable rw 0 2 lvds pll power down normal power down rw 0 3 rw 0 4 usb pll power down normal power down rw 0 5 src pll power down normal power down rw 0 6 cpu pll power down normal power down rw 0 7 src, pll2, ssc enable only valid when byte1 bit0 is 1 disable enable rw 1 byte 11 bit output(s) affected description / function 0 1 type power on 0 cpu_n0, lsb cpu clk = n* resolution rw 0 1 cpu_n1 see resolution table rw 1 2 cpu_n2 rw 1 3 cpu_n3 rw 0 4 cpu_n4 rw 1 5 cpu_n5 rw 0 6 cpu_n6 rw 0 7 cpu_n7, msb rw 1 byte 10 bit output(s) affected description / function 0 1 type power on 0 src smc0 src/pci ssc control rw 1 1 src smc1 see smc table rw 0 2 src smc2 rw 0 3 reserved rw 0 4 cpu smc0 cpu pll ssc control rw 1 5 cpu smc1 see smc table rw 0 6 cpu smc2 rw 0 7 reserved rw 0 byte 12 bit output(s) affected description / function 0 1 type power on 0 src_n0, lsb rw 0 1 src_n1 rw 1 2 src_n2 src f = n*src res olution rw 1 3 src_n3 resolution = 0.666667 rw 0 4 src_n4 100mhz n= 150 rw 1 5 src_n5 rw 0 6 src_n6 rw 0 7 src_n7, msb rw 1
commercial temperature range 10 IDTCV125 programmable flexpc clock for p4 processor byte 13 bit output(s) affected description / function 0 1 type power on 0 48mhzstr0 rw 0 1 48mhstr1 usb48mhz0 strength selection rw 0 2 refstr0 rw 0 3 refstr1 ref strength selection rw 0 4 pcistrc0 rw 0 5 pcistrc1 pci strength selection rw 0 6 pcifstr0 rw 0 7 pcifstr1 pcif strength selection rw 0 symbol parameter test conditions min. typ. max. unit v ih input high voltage 3.3v 5% 2 ? v dd + 0.3 v v il input low voltage 3.3v 5% v ss - 0.3 ? 0.8 v v ih _fs low voltage, high threshold for fsa.b.c test_mode 0.7 ? v dd + 0.3 v v il _fs low voltage, low threshold for fsa.b.c test_mode v ss - 0.3 ? 0.35 v i ih input high current v in = v dd ?5 ? 5 a i il1 input low current v in = 0v, inputs with no pull-up resistors ?5 ? ? a i il2 input low current v in = 0v, inputs with pull-up resistors ?200 ? ? a i dd3.3op operating supply current full active, c l = full load ? ? 400 ma i dd3.3pd powerdown current all differential pairs driven ? ? 70 ma all differential pairs tri-stated ? ? 12 f i input frequency (1) v dd = 3.3v ? 14.31818 ? mhz l pin pin inductance (2) ?? 7 nh c in logic inputs ? ? 5 c out input capacitance (2) output pin capacitance ? ? 6 pf c inx xtal_in ? ? 5 c outx xtal_out ? ? 12 t stab clock stabilization (2,3) from v dd power-up or de-assertion of pd to first clock ? ? 1.8 ms modulation frequency (2) triangular modulation 30 ? 33 khz t drive _src (2) src output enable after pci_stop# de-assertion ? ? 15 ns t drive _pd (2) cpu output enable after pd de-assertion ? ? 300 us t fall _pd (2) fall time of pd ? ? 5 ns t rise _pd (3) rise time of pd ? ? 5 ns t drive _cpu_stop# (2) cpu output enable after cpu_stop# de-assertion ? ? 10 us t fall _cpu_stop# (2) fall time of cpu_stop# ? ? 5 ns t rise _cpu_stop# (3) rise time of cpu_stop# ? ? 5 ns electrical characteristics - input / supply / common output parameters following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5% notes: 1. input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. 2. this parameter is guaranteed by design, but not 100% production tested. 3. see timing diagrams for timing requirements.
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 11 symbol parameter test conditions min. typ. max. unit z o current source output impedance (2) v o = v x 3000 ? ? ? v oh3 output high voltage i oh = -1ma 2.4 ? ? v v ol3 output low voltage i ol = 1ma ? ? 0.4 v v high voltage high (2) statistical measurement on single-ended signal using 660 ? 1150 mv v low voltage low (2) oscilloscope math function ?300 ? 150 v ovs max voltage (2) measurement on single-ended signal using absolute value ? ? 1150 mv v uds min voltage (2) ?300 ? ? v cross(abs) crossing voltage (abs) (2) 250 ? 550 mv d - v cross crossing voltage (var) (2) variation of crossing over all edges ? ? 140 mv ppm long accuracy (2,3) see t period min. - max. values ?300 ? 300 ppm 400mhz nominal / -0.5% spread 2.4993 ? 2.5133 333.33mhz nominal / -0.5% spread 2.9991 ? 3.016 266.66mhz nominal / -0.5% spread 3.7489 ? 3.77 t period average period (3) 200mhz nominal / -0.5% spread 4.9985 ? 5.0266 ns 166.66mhz nominal / -0.5% spread 5.9982 ? 6.032 133.33mhz nominal / -0.5% spread 7.4978 ? 7.54 100mhz nominal / -0.5% spread 9.997 ? 10.0533 96mhz nominal 10.4135 ? 10.4198 400mhz nominal / -0.5% spread 2.4143 ? ? 333.33mhz nominal / -0.5% spread 2.9141 ? ? 266.66mhz nominal / -0.5% spread 3.6639 ? ? 200mhz nominal / -0.5% spread 4.9135 ? ? t absmin absolute min period (2,3) 166.66mhz nominal / -0.5% spread 5.9132 ? ? ns 133.33mhz nominal / -0.5% spread 7.4128 ? ? 100mhz nominal / -0.5% spread 9.912 ? ? 96mhz nominal 10.1635 ? ? t r rise time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation (2) ? ? 125 ps d-t f fall time variation (2) ? ? 125 ps d t3 duty cycle (2) measurement from differential waveform 45 ? 55 % electrical characteristics - cpu, src, and dot96 0.7 current mode differential pair (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf notes: 1. src clock outputs run only at 100mhz. 2. this parameter is guaranteed by design, but not 100% production tested. 3. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range 12 IDTCV125 programmable flexpc clock for p4 processor symbol parameter test conditions min. typ. max. unit ppm static error (1,2) see tperiod min. - max. values ? ? 0 ppm t period clock period (2) 33.33mhz output nominal 29.991 ? 30.009 ns 33.33mhz output spread 29.991 ? 30.1598 v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns t f1 fall time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t sk1 skew (1) v t = 1.5v ? ? 500 ps t jcyc - cyc jitter, cycle to cycle (1) v t = 1.5v ? ? 500 ps electrical characteristics - pciclk / pciclk_f following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. electrical characteristics - cpu, src, and dot96 0.7 current mode differential pair, continued (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf symbol parameter test conditions min. typ. max. unit skew, cpu[1:0] (2) ? ? 100 t sk 3 skew, cpu2 (2) v t = 50% ? ? 250 ps skew, src (2) ? ? 250 jitter, cycle to cycle, cpu[1:0] (2) ?? 85 t jcyc - cyc jitter, cycle to cycle, cpu2 (2) measurement from differential waveform ? ? 100 ps jitter, cycle to cycle, src (2) ? ? 125 jitter, cycle to cycle, dot96 (2) ? ? 250 notes: 1. src clock outputs run only at 100mhz. 2. this parameter is guaranteed by design, but not 100% production tested.
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 13 symbol parameter test conditions min. typ. max. unit ppm static error (1,2) see tperiod min. - max. values ? ? 0 ppm t period clock period (2) 48mhz output nominal 20.8257 ? 20.834 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -29 ? ? ma v oh at max. = 3.135v ? ? -23 i ol output low current v ol at min. = 1.95v 29 ? ? ma v ol at max. = 0.4v ? ? 27 edge rate (1) rising edge rate 1 ? 2 v/ns edge rate (1) falling edge rate 1 ? 2 v/ns t r1 rise time (1) v ol = 0.8v, v oh = 2v 0.5 ? 1.2 ns t f1 fall time (1) v ol = 0.8v, v oh = 2v 0.5 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter, cycle to cycle ? ? 350 ps electrical characteristics, 48mhz, usb following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1) see tperiod min. - max. values ? ? 0 ppm t period clock period 14.318mhz output nominal 69.827 ? 69.855 ns v oh output high voltage (1) i oh = -1ma 2.4 ? ? v v ol output low voltage (1) i ol = 1ma ? ? 0.4 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r 1 rise time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns t f 1 fall time (1) v ol = 0.8v, v oh = 2v 0.3 ? 1.2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter, cycle to cycle (1) v t = 1.5v ? ? 1000 ps electrical characteristics - ref-14.318mhz following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf note: 1. this parameter is guaranteed by design, but not 100% production tested.
commercial temperature range 14 IDTCV125 programmable flexpc clock for p4 processor pci stop functionality the pci_stop# signal is on an active low input controlling pci and src outputs. if pcif[1:0] and src clocks can be set to be fr ee-running through smbus programming, they will ignore both the pci_stop# pin and the pci_stop register bit. pci_stop# assertion (transition from ?1? to ?0?) the clock samples the pci_stop# signal on a rising edge of pcif clock. after detecting the pci_stop# assertion low, all pci[6:0 ] and stoppable pcif[1:0] clocks will latch low on their next high to low transition. after the pci clocks are latched low, the src clock, (if set to sto ppable) will latch high at i ref * 6 (or tristate if byte 2 bit 6 = 1) upon its next low to high transition and the src# will latch low as shown below. pci_stop# - de-assertion the de-assertion of the pci_stop# signal is to be sampled on the rising edge of the pcif free running clock domain. after detec ting pci_stop# de-assertion, all pci[6:0], stoppable pcif[1:0] and stoppable src clocks will resume in a glitch free manner. pci_stop# pcif[1:0] 33mhz pci[3:0] 33mhz src 100mhz src# 100mhz t su pci_stop# pcif[1:0] 33mhz pci[3:0] 33mhz src 100mhz src# 100mhz t su t drive_src pci_stop# cpu cpu# src src# pcif/pci usb dot96 dot96# ref 1 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 0 normal normal i ref * 6 or float low low 48mhz normal normal 14.318mhz
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 15 cpu stop functionality the cpu_stop# signal is an active low input controlling the cpu outputs. this signal can be asserted asynchronously. cpu_stop# assertion (transition from ?1? to ?0?) asserting cpu_stop# pin stops all cpu outputs that are set to be stoppable after their next transition. when the smbus cpu_stop tri-state bit corresponding to the cpu output of interest is programmed to a ?0?, cpu output will stop cpu_true = high and cpu_complement = low. when the s mbus cpu_stop# tri-state bit corresponding to the cpu output of interest is programmed to a ?1?, cpu outputs will be tri-stated. cpu_stop# - de-assertion (transition from ?0? to ?1?) with the de-assertion of cpu_stop# all stopped cpu outputs will resume without a glitch. the maximum latency from the de-assert ion to active outputs is two to six cpu clock periods. if the control register tristate bit corresponding to the output of interest is programmed to ?1?, then the stopped cpu outputs will be driven high within 10ns of cpu_stop# de-assertion to a voltage greater than 200mv. cpu_stop# cpu cpu# cpu_stop# cpu cpu# cpu internal t drive _cpu_stop 10ns > 200mv cpu_stop# cpu cpu# src src# pcif/pci usb dot96 dot96# ref 1 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 0i ref * 6 or float low normal normal 33mhz 48mhz normal normal 14.318mhz
commercial temperature range 16 IDTCV125 programmable flexpc clock for p4 processor pd, power down pd is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. when pd is asserted high all clocks will be driven low before turning off the vco. in pd de-assertion all clocks will start without glitches. pd assertion pd cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 pd cpu cpu# src src# pcif/pci usb dot96 dot96# ref 0 normal normal normal normal 33mhz 48mhz normal normal 14.318mhz 1i ref * 2 or float float i ref * 2 or float float low low i ref * 2 or float float low
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 17 pd de-assertion pd cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms t drive_pwrdwn <300 s, <200mv
commercial temperature range 18 IDTCV125 programmable flexpc clock for p4 processor differential clock tristate to minimize power consumption, cpu[2:0] clock outputs are individually configurable through smbus to be driven or tristated dur ing pd and cpu_stop# mode and the src clock is configurable to be driven or tristated during pci_stop# and pd mode. each differential clock (src, c pu[2:0]) output can be disabled by setting the corresponding output?s register oe bit to ?0? (disable). disabled outputs are to be tristated regardles s of ?cpu_stop?, ?src_stop? and ?pd? register bit settings. signal pin pd pin cpu_stop# cpu_stoptristate bit pd tristate bit non-stoppable outputs stoppable outputs c p u 0 1 x x running running c p u 0 0 0 x running driven at i ref x 6 cpu 0 0 1 x running tristate cpu 1 x x 0 driven at i ref x 2 driven at i ref x 2 c p u 1 x x 1 tristate tristate notes: 1. each output has four corresponding control register bits; oe, pd, cpu_stop, and ?free running?. 2. i ref x 6 and i ref x 2 is the output current in the corresponding mode. 3. see control registers section for bit address. signal pin pd pin pci_stop# pci_stoptristate bit pd tristate bit non-stoppable outputs stoppable outputs src 0 1 x x running running src 0 0 0 x running driven at i ref x 6 src 0 0 1 x running tristate src 1 x x 0 driven at i ref x 2 driven at i ref x 2 src 1 x x 1 tristate tristate notes: 1. src output has four corresponding control register bits; oe, pd, src_stop, and ?free running?. 2. i ref x 6 and i ref x 2 is the output current in the corresponding mode. 3. see control registers section for bit address. signal pin pd pd tristate bit output dot96 1 x running dot96 0 0 driven at i ref x 2 dot96 0 1 tristate notes: 1. dot output has two corresponding control register bits; oe and pd. 2. i ref x 6 and i ref x 2 is the output current in the corresponding mode. 3. see control registers section for bit address. tristate dot96 clock control
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 19 symbol parameter min. typ. max. unit t r 1 clock rise time (1,2,3) 175 ? 700 ps t f 1 clock fall time (1,2,3) 175 ? 700 ps ? t r clock rise time variation (2,3,4) ? ? 125 ps ? t f clock fall time variation (2,3,4) ? ? 125 ps rise/fall matching (2,3,5) ?? 20% v high voltage high (2,3,6) 660 700 850 mv v low voltage low (2,3,7) -150 0 ? mv v cross(abs) crossing voltage (abs) (2,3,8,9,10) 250 ? 550 mv v cross(rel) crossing voltage (rel) (2,3,10,11) calc. ? calc. t otal ? v cross total variation of v cross over all edges (2,3,12) ? ? 140 mv t jcyc - cyc cycle-to-cycle jitter (2,13) ? ? 350 ps d t3 duty cycle (2,13) 45 ? 55 % v ovs maximum voltage allowed at output (overshoot) (2,3,14) ??v high + 0.3v v v uds minimum voltage allowed at output (undershoot) (2,3,15) -0.3 ? ? v v rb ringback margin (2,3) n/a ? 0.2 v lvds ac timing requirements following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c notes: 1. measured from v ol = 1.75v to v oh =0.525v. only valid for rising lvds and falling lvds#. signal must be monotonic through the v ol to v oh region for t rise and t fall . 2. test configuration is rs = 32.2 ? , rp = 49.9 ? , 2pf. 3. measurement taken from single-ended waveform. 4. measured with oscilloscope, averaging off, using min. max. statistics. variation is the delta between min. and max. 5. measured with oscilloscope, averaging off, the difference between the t rise (average) of lvds versus the t fall (average) of lvds#. 6. v high is defined as the statistical average high value as obtained by using the oscilloscope v high math function. 7. v low is defined as the statistical average low value as obtained by using the oscilloscope v low math function. 8. measured at crossing point where the instantaneous voltage value of the rising edge of lvds equals the falling edge of lvds#. 9. this measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is cro ssing. 10. the crossing point must meet the absolute and relative crossing point specifications simultaniously. 11. v cross (rel) min. and max. are derived using the following: v cross (rel) min. = 0.25v + 0.5 (v havg - 0.7v), v cross (rel) max. = 0.55v + 0.5 (0.7v - v havg ). 12. ? v cross is defined as the total variation of all crossing voltages of rising lvds and falling lvds#. this is the maximum allowed vari ance in v cross for any particular system. 13. measurement is taken from differential waveform. 14. overshoot is defined as the absolute value of the maximum voltage. 15. undershoot is defined as the absolute value of the minimum voltage.
commercial temperature range 20 IDTCV125 programmable flexpc clock for p4 processor 96mhz 100mhz spread min. max. min. max. unit 0% (no spread) 10.406 10.427 9.99 10.01 ns 0.8% down-spread 10.406 10.511 9.99 10.09 ns 1% down-spread 10.406 10.531 9.99 10.11 ns 1.25% down-spread 10.406 10.557 9.99 10.135 ns 1.5% down-spread 10.406 10.583 9.99 10.16 ns 1.75% down-spread 10.406 10.61 9.99 10.185 ns 2% down-spread 10.406 10.636 9.99 10.21 ns 2.5% down-spread 10.406 10.688 9.99 10.26 ns 3% down-spread 10.406 10.74 9.99 10.31 ns 0.3% down-spread 10.375 10.458 9.96 10.04 ns 0.4% down-spread 10.365 10.469 9.95 10.05 ns 0.5% down-spread 10.354 10.479 9.94 10.06 ns 0.6% down-spread 10.344 10.49 9.93 10.07 ns 0.8% down-spread 10.323 10.511 9.91 10.09 ns 1% down-spread 10.302 10.531 9.89 10.11 ns 1.25% down-spread 10.276 10.557 9.865 10.135 ns 1.5% down-spread 10.25 10.583 9.84 10.16 ns lvds average period, tperiod (1,2,3,4) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c notes: 1. test configuration is rs = 32.2 ? , rp = 49.9 ? , 2pf. 2. the average period over any 1 s period of tiime must be greater than the minimum and less than the maximum specified period. 3. measurement is taken from differential waveform. 4. calculated using a 0.1% accuracy in spread modulation. assumes 300ppm long term accuracy on clkin. single-ended measurement point for t rise and t fall v oh = 0.525v vc ross v ol = 0.175v t rise (lvds) t fall (lvds#) lvds# lvds
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 21 symbol parameter min. typ. max. unit t pzl output enable delay (all outputs) (1) 0?10 s t pzh t plz output disable delay (all outputs) (1) 0?10 s t phz t stable all clock stabilization from power-up (2) ??3ms t spread setting period for spread selection change (2,3) ??3ms miscellaneous ac timing requirements following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c notes: 1. these specifications apply to the lvds and smbus pins. these pins must be tri-stated when p wrdwn is asserted. lvds is driven differential when p wrdwn is de-asserted unless it is disabled. 2. the time specified is from when v dd achieves its nominal operating level (typical condition v dd = 3.3v) and p wrdwn is de-asserted until the frequency output is stable and operating within specification. 3. the time specified is measured from the spread selection change or output frequency change until the lvds clock is operating at the new spread modulation and frequency. if there is another change in spread selection or output frequency during the t spread settling period, then the settling period start resets to the most recent change in spread selection and output frequency.
commercial temperature range 22 IDTCV125 programmable flexpc clock for p4 processor pwrdwn (power down) clarification p wrdwn assertion p wrdwn de-assertion p wrdwn clock vco lvds lvds# t phz on off p wrdwn clock vco lvds lvds# t pzh off starting stable t stable v dd
commercial temperature range IDTCV125 programmable flexpc clock for p4 processor 23 lvds system implementation clock rs rp unit lvds clock 33.2 49.9 ? 5% 1% test load board configuration tla tlb 49.9 ? 1% 49.9 ? 1% 33 ? 5% 33 ? 5% 2pf 5% 2pf 5% clock clock# lvds lvds# cv125 475 ? 1%
commercial temperature range 24 IDTCV125 programmable flexpc clock for p4 processor ordering information xxx xx package pa pag thin small shrink outline package tssop - green programmable flexpc clock for p4 processor 125 device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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